This application claims the benefit of a Japanese Patent Application No. 2000-054879 filed Feb. 29, 2000, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to semiconductor devices and semiconductor device testing methods, and more particularly to a semiconductor device having a test mode, and to a semiconductor device testing method for testing such a semiconductor device.
Generally, when guaranteeing functions and performances of semiconductor devices such as semiconductor memory devices at the time of forwarding the semiconductor devices or, when a user checks abnormalities of the semiconductor device, a command is input to the semiconductor device to switch an operation mode thereof to a test mode, so as to carry out various kinds of tests. The switching of the operation mode of the semiconductor device from a normal mode to the test mode is often referred to as a test mode entry.
2. Description of the Related Art
In a conventional synchronous dynamic random access memory (SDRAM), the test mode entry is made by inputting a command to the SDRAM in synchronism with an external clock, for example, and a timing control can be made with ease. In addition, in a case where the command is determined by a predetermined combination of signals such as a chip select signal and an address strobe signal, the test mode entry is erroneously made if the predetermined combination of the signals occurs accidentally. Accordingly, it is possible to use a command signal exclusively for switching the operation mode of the semiconductor device to the test mode, but in this case, it is necessary to provide an input pin exclusively for receiving the command signal. But the provision of this additional input pin for exclusively receiving the command signal increases the circuit scale of the SDRAM, thereby making it difficult to improve the integration density of the SDRAM.
On the other hand, in an asynchronous DRAM, it is not possible to employ a test mode entry system of the type employed in the SDRAM, because the asynchronous DRAM does not use an external clock. Thus, in one example of the conventional asynchronous DRAM, the test mode entry is made by applying a super-high voltage which is higher than a voltage which is normally applied with respect to the asynchronous DRAM. However, when this test mode entry system is employed, it is necessary to provide a circuit for detecting the super-high voltage in the asynchronous DRAM. As a result, the circuit scale of the asynchronous DRAM increases, and it becomes difficult to improve the integration density of the asynchronous DRAM. Furthermore, when the super-high voltage is used, the number of kinds of voltages applied to the asynchronous DRAM increases, and it becomes necessary to carry out a process such as waiting for the super-high voltage to be released, thereby making the testing process complex.
Therefore, in the conventional semiconductor devices, there were problems in that it is impossible to simply and positively make the test mode entry, regardless of whether the semiconductor device is the synchronous type or the asynchronous type, and without increasing the circuit scale of the circuits within the semiconductor device or sacrificing the integration density of the semiconductor device.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and semiconductor device testing method, in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device and a semiconductor device testing method, which can simply and positively make a test mode entry, regardless of whether the semiconductor device is the synchronous type or the asynchronous type, and without increasing the circuit scale of circuits within the semiconductor device or sacrificing the integration density of the semiconductor device.
Still another object of the present invention is to provide a semiconductor device having a test mode for testing the semiconductor device, comprising a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal. According to the semiconductor device of the present invention, it is possible to simply and positively make a test mode entry, regardless of whether the semiconductor device is the synchronous type or the asynchronous type, and without increasing the circuit scale of circuits within the semiconductor device or sacrificing the integration density of the semiconductor device.
In the semiconductor device, the dummy command signals may be formed by a predetermined combination of a plurality of command signals. Further, the circuit may include a plurality of registers which successively store the dummy command.
A further object of the present invention is to provide a semiconductor device testing method for testing a semiconductor device by switching an operation mode of the semiconductor device to a test mode, comprising the steps of (a) outputting a first signal based on dummy command signals which are input a plurality of times, and (b) outputting a second signal which instructs an entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal. According to the semiconductor device testing method of the present invention, it is possible to simply and positively make a test mode entry, regardless of whether the semiconductor device is the synchronous type or the asynchronous type, and without increasing the circuit scale of circuits within the semiconductor device or sacrificing the integration density of the semiconductor device.
In the semiconductor device testing method, the dummy command signals may be formed by a predetermined combination of a plurality of command signals.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.